1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices and methods for manufacturing same. In one aspect, the present invention relates to the fabrication of high-k metal gate devices for different voltage level transistors integrated on a single substrate or chip.
2. Description of the Related Art
Non-volatile memory devices, such as EEPROM and flash memory, are used in computers and other electronic devices to store data and/or programming instructions that can be electrically erased and reprogrammed and that must be saved when power is removed. Embedded non-volatile memory (NVM) has become increasingly important in applications ranging from data and code storage to circuit trimming and customization. However, the integration of non-volatile memory with CMOS transistors on a single chip can create a number of integration difficulties and challenges as the different materials and/or fabrication processes conflict with one another when the semiconductor fabrication processes used to form high voltage (HV) transistors (which handle high voltages (e.g., 12V or higher) that are suitable for programming non-volatile memory cells) or dual-gate oxide (DGO) devices (which are higher voltage, low-leakage devices suitable for battery-powered devices) are not compatible with the processes used to fabricate low voltage (LV) transistors (which are used for low-voltage logic circuits, such as microcontrollers, SRAMs, ROMs). These challenges and difficulties can be exacerbated as device scaling increases and new device structures, such as metal gate electrodes, are replacing conventional polysilicon gate electrodes used with CMOS technology. For example, the integration of medium voltage and high voltage devices into a high-k metal gate (HKMG) process flow can result in the formation of shallow trench isolation (STI) divots in the low voltage device areas that are masked off during gate dielectric formation. The integration of different HKMG device process flows can also result in other challenges, such as formation of high voltage NMOS and PMOS transistor devices with gate dielectric layers having different thicknesses when oxide growth is employed to form the gate dielectric layers. These challenges, among others, complicate the process of fabricating CMOS devices with embedded non-volatile memory, increasing the manufacturing costs and the difficulty of achieving high performance levels.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.